1. Field of the Invention
The disclosed invention relates to solid-state image sensors, and more specifically to CMOS image sensors that have two or more photo-sites stacked above each other resulting in a compact pixel layout having high sensitivity and low dark current.
2. Description of Related Art
Typical image sensors sense light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. After completion of the integration cycle collected charge is converted into a voltage, which is supplied to the output terminals of the sensor. In CMOS image sensors the charge to voltage conversion is accomplished directly in the pixels themselves and the analog pixel voltage is transferred to the output terminals through various pixel addressing and scanning schemes. The analog signal can also be converted on-chip to a digital equivalent before reaching the chip output. The pixels have incorporated in them a buffer amplifier, typically the source follower, which drives the sense lines that are connected to the pixels by suitable addressing transistors. After charge to voltage conversion is completed and the resulting signal transferred out from the pixels, the pixels are reset in order to be ready for accumulation of new charge. In pixels that are using Floating Diffusion (FD) as the charge detection node, the reset is accomplished by turning on a reset transistor that momentarily conductively connects the FD node to a voltage reference. This step removes collected charge. However, it generates kTC-reset noise as is well known in the art. kTC noise has to be removed from the signal by the Correlated Double Sampling (CDS) signal processing technique in order to achieve a desired low noise performance. Typical CMOS sensors that utilize the CDS concept need to have four transistors (4T) in the pixel. An example of the 4T pixel circuit can be found in U.S. Pat. No. 5,991,184 to Guidash. By introducing switching pulses into the Vdd bias line it is possible to eliminate the select transistor from the pixel and achieve the CDS operation with only three transistors (3T) in the pixel as described by Masahiro Kasano in: “A 2.0 um Pixel Pitch MOS Image Sensor with an Amorphous Si Film Color Filter.” Digest of Technical Papers ISCC, vol. 48, February 2005, pp. 348-349. The larger number of transistors in each pixel becomes a problem when the pixel size needs to be reduced in order to build low cost and high-resolution image sensors. Standard 3T pixels cannot use the CDS concept for kTC noise suppression and some other means must be used to minimize the adverse effects of this noise.
The color sensing in most single chip CMOS and CCD image sensors is accomplished by placing various light absorbing and color transmitting filters on top of the pixels in a predetermined pattern. The different pixels in a given pixel sub-group or a sub-array thus become sensitive only to a certain wavelength band of the spectrum. The pixel sub-groups thus form single color super pixels. The signal from the “color sensitive” sub-group pixels is then used to construct the color super-pixel signal using various interpolating and color signal processing methods in an attempt to recover the resolution that has been unavoidably lost in this scheme. An example of a typical color pixel pattern can be found for example in U.S. Pat. No. 3,971,065 to Bayer. Another example of the color filter arrangement can be found in the paper by Masahiro Kasano already mentioned above. All these approaches to color sensing have the principal disadvantage of sacrificing resolution as mentioned above and sacrificing sensitivity by the absorption of light in the various color filters.
An ingenious solution to this problem has been found and is already pursued by several companies, for example, by Foveon as can be learned in U.S. Pat. No. 6,894,265 to Merrill. In this approach three photodiodes are placed on top of each other inside the silicon bulk and the light generated carriers are collected at different depths depending on the impinging light wavelength. The voltage signal is then obtained by connecting these buried photodiodes to circuits located on top of the silicon chip surface where charge is sensed, processed, and reset in the usual way. The advantage of this approach is that no resolution is sacrificed by placing the color filter covered pixels side by side and no photons need to be absorbed in the color filters. However, it is not easy to form the photodiodes that are buried deep in the silicon bulk and also it is not without problem to sense charge collected in the buried photodiodes by circuits located on top of the silicon chip without adding noise.
In FIG. 1 the drawing 100 represents a cross section of the prior art pinned photodiode light-sensing element with a simplified schematic diagram of the associated pixel circuit. The pixel has the ability to separate charge according to its depth of generation and thus sense color. The p type silicon substrate 101 has Shallow Trench Isolation (STI) regions 102 etched in its surface and filled with a silicon dioxide 103. The silicon dioxide 103 also covers the entire surface of the pixel as in common in this technology. A shallow p+ doped region 104 passivates the walls and the bottom of the STI regions 102 as well as the surface of the pixel to minimize dark current generation. In this pixel, however, a p+ doped barrier 123 has been placed at a depth Xb 125 into the pixel. This barrier 123 separates the pixel into two distinct regions or photo-sites. The photo-generated charge 108 that is generated within the depth Xb (typically depleted) is collected and stored in the n type doped region 105 of the pinned photodiode. Charge 110 that is generated below the barrier 123 in the un-depleted region of the silicon diffuses around the barrier 123 into the edge of the depletion region 109 and is collected and stored in the FD 106. Since the depletion region has been made shallower than the depletion region of the typical pixel in this particular pixel concept, it is necessary to add charge cross talk barriers 124 into the structure to minimize the lateral charge diffusion and thus the pixel cross talk. Other means of cross talk prevention, such as making the STI isolation trenches deeper are well known to those skilled in the art. This pixel thus has the ability to detect and separately store charge that has been generated at different depths, according to the wavelength of light that has generated it, and thus inherently sense color without the necessity of light absorbing filters on top of the pixel. The circuit for processing the signals from this pixel is identical to the circuit of other 4T pixel designs. Transistor 118 resets the node 113 after transistor 114 has sensed its potential. Transistor 115 is the select transistor that connects the pixel signal to the column sense line 116. After charge collected in the FD region 106, which corresponds to light with longer wavelengths, has been sensed and reset the transfer gate (Tx) 107 is briefly pulsed to transfer charge collected in the pinned photodiode to the FD region 106. This charge corresponds to light with shorter wavelengths. The remaining control signals are supplied to the pixel via the reset gate bus (Rx) 120 and the address gate bus (Sx) 121. The conversion gain of this pixel is adjusted by selecting a suitable value for the capacitor (Cs) 119 that is connected between the node 113 and the node (Vdd) 117. When photons 122 impinge on the pixel, they penetrate into the silicon bulk depending on their wavelength and create the corresponding electron-hole pairs at that particular depth. This pixel thus has the ability to sense charge according to its depth of generation and thus sense color. As has been made clear in the above detailed description, this is accomplished without the necessity of forming an additional n type bulk charge storage region under the pinned photodiode. Only a potential barrier formed by the p+ type doped layer 123, which does not store charge has been added to the pixel. Charge generated below this barrier 123 is diverted away from the pinned photodiode and flows into a second storage region located at the surface of the silicon substrate. U.S. Pat. No. 7,737,475 to Hynecek, incorporated herein by reference, describes in more detail the above approach for building the CMOS color image sensors, which addresses these difficulties and provides a simpler and more practical solution for color sensing with less resolution loss than in the conventional approach and with minimum loss of light sensitivity. By placing the special potential barrier under the conventional pinned photodiode it is possible do divert the photo-generated carriers from the deep bulk region and direct them to flow in a narrow region to the surface of the silicon where they can be easily collected and stored for subsequent readout. The carriers from the bulk can thus be conveniently stored in a suitable structure next to the carriers generated and stored in the conventional photodiode near the silicon surface. It is thus not necessary to form buried photodiodes, collect and store charge deep in the bulk of the silicon, which is then difficult to access, read, and reset. It is also possible to place the special potential barrier in different depths in different pixels and thus make the pixels sensitive to different light spectral regions. Each pixel can thus provide two or more differently coded color signals instead of one. The resolution is not sacrificed as much as in the conventional approach and the light sensitivity is also not sacrificed, since no color absorbing filters, or not as many color absorbing filters are used. Storing all the photo-generated charge close to the silicon chip surface makes it possible to share some of the low noise readout and reset circuitry that is located there and thus achieve high performance with very small pixel sizes. This approach is thus much simpler and easier to implement in the current CMOS technology with high yield. However, it is important that the surface located second charge storage structures do not generate an excessive amount of dark current. This has not been achieved in the above cited patent to Hynecek where charge from the deep photo-site is stored on the FD or in the Source Follower MOS gate structure. Both of these charge storage structures are known to generate a large amount of dark current in comparison to a pinned photodiode. In addition the reset of the FD charge storage region is known to generate kTC noise.